HDI Layout Guidelines

High Density Interconnect (HDI) can be regarded as an innovation of traditional printed circuit boards (PCB). The reason is that HDI makes many systems have high component counts and net counts. The applications of HDI include smartphones, powerful computers, networking equipment, aerospace, etc. In order to achieve the purpose of packing more components on a small board, designers need to tackle the following challenges:

  • The limited workspace of the board
  • How to achieve smaller component footprints
  • The dense spacing issues between components and other physical features
  • The increased signal propagation delay caused by longer traces
  • More trace routes
  • More components on either side of the board

Component footprints refer to patterns on the PCB layout that indicates the location of components which will be soldered during the assembly. Designers try to make the component footprints smaller to reduce the space occupied. According to IPC-7351, footprints are generally divided into three categories:

  • Density Level A: it is suitable for low-density products and takes up more board area than the other two
  • Density Level B: it is suitable for products with a moderate level of component density
  • Density Level C: it is for HDI and takes up less space than the other two

The HDI with Small Footprints

Figure 1: The HDI with Small Footprints

For an HDI layout, designers generally include the following features to accommodate fine-pitch components:

  • Microvias
  • Thinner traces
  • Higher layer count
  • Lower signal levels

According to the design requirements of HDI, the microvias which are mechanically or laser drilled can be either staggered or stacked. These various via configurations are mainly for ball grid array (BGA) components with different pitches. In addition, the choice of vias determines the duration, steps and cost of the process. As for thinner traces, they allow a higher trace density to establish a connection between vias and each layer. Compared to traditional PCB boards, the HDI layer count can reach 30 or even more layers. In order to avoid ESD caused by the high field strength between adjacent lines and the excessive temperature rise in conductors, the HDI is not used for high voltage or high current. All in all, when optimizing cost and manufacturing, all these features need to take into considerations.

Microvias in the HDI Layout

Figure 2: Microvias in the HDI Layout

In the HDI layout design process, component selection is time-consuming because the mounted components on the board determine the trace width, trace requirements, drilling size and stack-up. The optimization between the limited available area on the HDI and the number of layers will provide the ideal component size since the smaller usable area limits the size of the component footprints and fine-pitch components require more layers for routing. If the placement of components is wrong, it will affect the operation and efficiency of the board. No EMI and parasitic capacitance or inductance should occur between the adjacent pins or pads. Thus, before placing the components on the PCB, the possibility of signal integrity improvement must be studied accordingly. In addition, the component placement also affects the via locations. Therefore, if the positions of the vias are not symmetrical, the entire circuit board will receive uneven forces, which may even affect the strength of the circuit board. The following four factors determine the selection of HDI components:

  • Availability
  • Traceability
  • Performance
  • Packaged or land pattern

SMD packages with small footprints are an option for resistors and capacitors in HDI. But components such as transformers, quartz crystal resonators, ceramic resonators, filters, etc. are not available in these exceedingly small package styles. BGA packages are another option for HDI.  Pins are located below the surface of the components, the space consumption of these components is reduced.

SMD packages in HDI

Figure 3: SMD packages in HDI

BGA packages in HDI

Figure 4: BGA packages in HDI


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